1. Field of the Invention
The present invention relates to phase locked loop synthesizer (PLL) circuits, and more specifically to a method and apparatus for resuming the operation of a PLL that has entered a hang up status.
2. Related Art
Phase locked loop synthesizer (PLL) circuits are often used to generate output signals synchronous with an input reference signal. Ideally, the output signal has a frequency equaling a desired multiple of the input reference signal. In addition, the output signal is ideally in phase with the input reference signal. The signals generated by PLLs are used to drive various external circuits as is well known in the relevant arts.
In some situations, PLL circuits enter a hang up status. For example, a PLL circuit may enter a hang up status either during startup or during later operation due to variations and/or imperfections in supply voltage (often referred to as Vdd) as is well known in the relevant arts. PLL circuits generally do not generate the desired output signals when in hang up status. Typically, the output generated by the PLL circuit in hang up status is at a xe2x80x98stuckxe2x80x99 condition, i.e., the output remains at a substantially constant voltage level (e.g., representing a logical 1 or 0).
Hang up status (of a PLL) is often undesirable at least in that any external circuits driven by the PLL can become non-operational. Therefore, what is needed is a method and apparatus to resume the operation of a PLL that has entered a hang up status.